diff options
author | huang lin <hl@rock-chips.com> | 2016-08-22 11:36:17 +0800 |
---|---|---|
committer | Jianqun Xu <jay.xu@rock-chips.com> | 2016-08-25 19:04:37 +0800 |
commit | 00fed37569b977b313ca2064d5c293f040ac90ab (patch) | |
tree | 6004bbb0c4bd2b59c406772a299fe506d23cb8b9 /drivers/clk/rockchip/clk.c | |
parent | 8f8121632183f20bd6002961c361d2448198a03b (diff) |
FROMLIST: clk: rockchip: add new clock-type for the ddrclk
On new rockchip platform(rk3399 etc), there have dcf controller to
do ddr frequency scaling, and this controller will implement in
arm-trust-firmware. We add a special clock-type to handle that.
Change-Id: I9e15dd9e01ab1c51a639a6a59391cd5e0de383b7
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk.c')
-rw-r--r-- | drivers/clk/rockchip/clk.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 8e1f270ad81e..efd4688caf61 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -487,6 +487,15 @@ void __init rockchip_clk_register_branches( list->gate_offset, list->gate_shift, list->gate_flags, flags, &ctx->lock); break; + case branch_ddrc: + clk = rockchip_clk_register_ddrclk( + list->name, list->flags, + list->parent_names, list->num_parents, + list->muxdiv_offset, list->mux_shift, + list->mux_width, list->div_shift, + list->div_width, list->div_flags, + ctx->reg_base, &ctx->lock); + break; } /* none of the cases above matched */ |