diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2018-12-20 15:05:31 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-12-21 11:15:42 +0800 |
| commit | b2f84f61114f766049ceb304470d1998ec77de1b (patch) | |
| tree | d602ef41ed1113d1fdbe253052cde4bd987a1580 /drivers/clk/rockchip/clk-rk3368.c | |
| parent | 2521529422b974738a97308c82e6f953d06bf309 (diff) | |
clk: rockchip: rk3368: add FRAC_MAX_PRATE limit for spdif/uart/i2s
Change-Id: I24d365f5cb97da8974a0f718b5b56b6ffdaae27b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3368.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3368.c | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c index 86238e6c7371..0201713f7374 100644 --- a/drivers/clk/rockchip/clk-rk3368.c +++ b/drivers/clk/rockchip/clk-rk3368.c @@ -20,6 +20,9 @@ #include "clk.h" #define RK3368_GRF_SOC_STATUS0 0x480 +#define RK3368_I2S_FRAC_MAX_PRATE 600000000 +#define RK3368_UART_FRAC_MAX_PRATE 600000000 +#define RK3368_SPDIF_FRAC_MAX_PRATE 600000000 enum rk3368_plls { apllb, aplll, dpll, cpll, gpll, npll, @@ -405,7 +408,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(28), 0, RK3368_CLKGATE_CON(6), 2, GFLAGS, - &rk3368_i2s_8ch_fracmux, 0), + &rk3368_i2s_8ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE), COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0, RK3368_CLKSEL_CON(27), 15, 1, MFLAGS, RK3368_CLKGATE_CON(6), 0, GFLAGS), @@ -417,7 +420,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(32), 0, RK3368_CLKGATE_CON(6), 5, GFLAGS, - &rk3368_spdif_8ch_fracmux, 0), + &rk3368_spdif_8ch_fracmux, RK3368_SPDIF_FRAC_MAX_PRATE), GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT, RK3368_CLKGATE_CON(6), 6, GFLAGS), COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0, @@ -426,7 +429,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(54), 0, RK3368_CLKGATE_CON(5), 14, GFLAGS, - &rk3368_i2s_2ch_fracmux, 0), + &rk3368_i2s_2ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE), GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT, RK3368_CLKGATE_CON(5), 15, GFLAGS), @@ -627,7 +630,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(34), 0, RK3368_CLKGATE_CON(2), 1, GFLAGS, - &rk3368_uart0_fracmux, 0), + &rk3368_uart0_fracmux, RK3368_UART_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0, RK3368_CLKSEL_CON(35), 0, 7, DFLAGS, @@ -635,7 +638,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(36), 0, RK3368_CLKGATE_CON(2), 3, GFLAGS, - &rk3368_uart1_fracmux, 0), + &rk3368_uart1_fracmux, RK3368_UART_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0, RK3368_CLKSEL_CON(39), 0, 7, DFLAGS, @@ -643,7 +646,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(40), 0, RK3368_CLKGATE_CON(2), 7, GFLAGS, - &rk3368_uart3_fracmux, 0), + &rk3368_uart3_fracmux, RK3368_UART_FRAC_MAX_PRATE), COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0, RK3368_CLKSEL_CON(41), 0, 7, DFLAGS, @@ -651,7 +654,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT, RK3368_CLKSEL_CON(42), 0, RK3368_CLKGATE_CON(2), 9, GFLAGS, - &rk3368_uart4_fracmux, 0), + &rk3368_uart4_fracmux, RK3368_UART_FRAC_MAX_PRATE), COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0, RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS, |