diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-09-21 15:11:23 +0800 |
|---|---|---|
| committer | Finley Xiao <finley.xiao@rock-chips.com> | 2018-09-21 15:12:54 +0800 |
| commit | d66b15530750303b77517c0bbfe2102b4c8b9215 (patch) | |
| tree | 3943948bd5d55a0a3652e5daf7b43e0bd54c5c20 /drivers/clk/rockchip/clk-rk3308.c | |
| parent | 7b544df052cffbe90c5908119e036f405031218e (diff) | |
clk: rockchip: rk3308: Fix spi clock's name
Change-Id: Id15d23786eed3e0105ad4f53858421a222e680d9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3308.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3308.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c index 76945c491f81..4d423d333878 100644 --- a/drivers/clk/rockchip/clk-rk3308.c +++ b/drivers/clk/rockchip/clk-rk3308.c @@ -414,13 +414,13 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = { RK3308_CLKSEL_CON(75), 14, 2, MFLAGS, 0, 7, DFLAGS, RK3308_CLKGATE_CON(15), 1, GFLAGS), - COMPOSITE(SCLK_SPI0, "clk_isp0", mux_dpll_vpll0_xin24m_p, 0, + COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0, RK3308_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 7, DFLAGS, RK3308_CLKGATE_CON(3), 2, GFLAGS), - COMPOSITE(SCLK_SPI1, "clk_isp1", mux_dpll_vpll0_xin24m_p, 0, + COMPOSITE(SCLK_SPI1, "clk_spi1", mux_dpll_vpll0_xin24m_p, 0, RK3308_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 7, DFLAGS, RK3308_CLKGATE_CON(3), 3, GFLAGS), - COMPOSITE(SCLK_SPI2, "clk_isp2", mux_dpll_vpll0_xin24m_p, 0, + COMPOSITE(SCLK_SPI2, "clk_spi2", mux_dpll_vpll0_xin24m_p, 0, RK3308_CLKSEL_CON(32), 14, 2, MFLAGS, 0, 7, DFLAGS, RK3308_CLKGATE_CON(3), 4, GFLAGS), |