diff options
| author | Jacob Chen <jacob2.chen@rock-chips.com> | 2017-01-18 13:50:27 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2017-01-19 10:08:10 +0800 |
| commit | aa4ac52a9791176aa758cb80812c9a14145f9357 (patch) | |
| tree | d52cd02c2d53bd4cc24a560fb8364a02438e1755 /drivers/clk/rockchip/clk-rk3288.c | |
| parent | 01afa13ceb6b3e695c1a886b25f97a28c5c8d4d7 (diff) | |
clk: rk3288: correct cif_out to vip_out
we already have vip_src and sclk_vip_out defined, which are the clocks
we add as cif_out, so let's correct it.
Change-Id: I952b1490a882d290aa36d9629aeb32eee22ce8b3
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3288.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index d5989eac06b5..f1300fd5a93f 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -193,7 +193,6 @@ PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" }; PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" }; PNAME(mux_vip_out_p) = { "vip_src", "xin24m" }; -PNAME(mux_cifout_p) = { "cif_src", "xin24m" }; PNAME(mux_mac_p) = { "mac_pll_src", "ext_gmac" }; PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" }; PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" }; @@ -449,12 +448,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, RK3288_CLKGATE_CON(3), 15, GFLAGS), - COMPOSITE_NOGATE(0, "cif_src", mux_pll_src_cpll_gpll_p, 0, - RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, 9, 5, DFLAGS), - COMPOSITE_NODIV(SCLK_CIFOUT, "sclk_cifout", mux_cifout_p, 0, - RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, - RK3288_CLKGATE_CON(3), 7, GFLAGS), - GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0, RK3288_CLKGATE_CON(5), 12, GFLAGS), GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0, @@ -476,7 +469,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0, RK3288_CLKSEL_CON(26), 8, 1, MFLAGS, RK3288_CLKGATE_CON(3), 7, GFLAGS), - COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0, + COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0, RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS), DIV(0, "pclk_pd_alive", "gpll", 0, |