diff options
author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-03-28 15:12:24 +0800 |
---|---|---|
committer | Tao Huang <huangtao@rock-chips.com> | 2018-04-02 17:01:54 +0800 |
commit | 4186a0e4239b087c163acdbdd03e7411001966f2 (patch) | |
tree | 293123584694eedee1ea8a4e23aa1b6f95122c46 /drivers/clk/rockchip/clk-rk3228.c | |
parent | ec9e751d33630b4e3c81b5f46c784bae011d1837 (diff) |
clk: rockchip: Add supprot to limit input rate for fractional divider
From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3228.c')
-rw-r--r-- | drivers/clk/rockchip/clk-rk3228.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index b78dc2accb61..0d5cb278b8b4 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -405,7 +405,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(8), 0, RK2928_CLKGATE_CON(0), 4, GFLAGS, - &rk3228_i2s0_fracmux), + &rk3228_i2s0_fracmux, 0), GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, RK2928_CLKGATE_CON(0), 5, GFLAGS), @@ -415,7 +415,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(7), 0, RK2928_CLKGATE_CON(0), 11, GFLAGS, - &rk3228_i2s1_fracmux), + &rk3228_i2s1_fracmux, 0), GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, RK2928_CLKGATE_CON(0), 14, GFLAGS), COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0, @@ -428,7 +428,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(30), 0, RK2928_CLKGATE_CON(0), 8, GFLAGS, - &rk3228_i2s2_fracmux), + &rk3228_i2s2_fracmux, 0), GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, RK2928_CLKGATE_CON(0), 9, GFLAGS), @@ -438,7 +438,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(20), 0, RK2928_CLKGATE_CON(2), 12, GFLAGS, - &rk3228_spdif_fracmux), + &rk3228_spdif_fracmux, 0), GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(1), 3, GFLAGS), @@ -473,15 +473,15 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(17), 0, RK2928_CLKGATE_CON(1), 9, GFLAGS, - &rk3228_uart0_fracmux), + &rk3228_uart0_fracmux, 0), COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(18), 0, RK2928_CLKGATE_CON(1), 11, GFLAGS, - &rk3228_uart1_fracmux), + &rk3228_uart1_fracmux, 0), COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, RK2928_CLKSEL_CON(19), 0, RK2928_CLKGATE_CON(1), 13, GFLAGS, - &rk3228_uart2_fracmux), + &rk3228_uart2_fracmux, 0), COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS, |