diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2017-03-01 22:00:42 +0100 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2017-06-05 16:10:51 +0800 |
| commit | f6e7fcae9814bc0c35ca71cd2ea31a27a33bac74 (patch) | |
| tree | 53ed748c7154a8f033fdd7caeb68f2b89fbfa1f8 /drivers/clk/rockchip/clk-rk3036.c | |
| parent | 9f0f403d8174f3df47c9d9d6e7094c8094765148 (diff) | |
UPSTREAM: clk: rockchip: Make uartpll a child of the gpll on rk3036
The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.
This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
commit f8ba2d68e54fbca340ad0fce97397291ba9637bc)
Change-Id: Ia8683d7b49523284043457727665d7e58d1551ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3036.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3036.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index 6cdb0a24c066..9ee3ac142d98 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -446,6 +446,13 @@ static void __init rk3036_clk_init(struct device_node *np) return; } + /* + * Make uart_pll_clk a child of the gpll, as all other sources are + * not that usable / stable. + */ + writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), + reg_base + RK2928_CLKSEL_CON(13)); + ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); |