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authorCaesar Wang <wxt@rock-chips.com>2017-11-17 14:49:16 +0800
committerTao Huang <huangtao@rock-chips.com>2017-11-17 18:01:59 +0800
commit3ee9576c62df180ef4ab3af85521624d3a380acc (patch)
treed7fe56df61b4e2a17b53538a37786359ac9fa3ac /drivers/clk/rockchip/clk-rk3036.c
parent66a11945dafd2680a158abc4f268481b0a64f55d (diff)
clk: rockchip: protect the armclk for rk3036
Some clocks may get disabled as a side effect of another clock being disabled, because have no consumers. Says the dclk_hdmi's parent may change from apll to gpll, but the apll's son clocks are very less. Change-Id: I4fb4e5fdf83a8f73979b50dbcf4f3e4543896fcf Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3036.c')
-rw-r--r--drivers/clk/rockchip/clk-rk3036.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 320031da285b..252cb770854b 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -431,6 +431,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
};
static const char *const rk3036_critical_clocks[] __initconst = {
+ "armclk",
"aclk_cpu",
"aclk_peri",
"hclk_peri",
@@ -497,14 +498,14 @@ static void __init rk3036_clk_init(struct device_node *np)
RK3036_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3036_clk_branches,
ARRAY_SIZE(rk3036_clk_branches));
- rockchip_clk_protect_critical(rk3036_critical_clocks,
- ARRAY_SIZE(rk3036_critical_clocks));
-
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
&rk3036_cpuclk_data, rk3036_cpuclk_rates,
ARRAY_SIZE(rk3036_cpuclk_rates));
+ rockchip_clk_protect_critical(rk3036_critical_clocks,
+ ARRAY_SIZE(rk3036_critical_clocks));
+
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);