diff options
| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-03-09 10:37:03 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2016-03-15 17:24:38 +0800 |
| commit | 35bba3204b5026a9208fbd658515aca9e3d10cdd (patch) | |
| tree | 5a5e022641d02fac14b5d01112b5550a342e9d5e /drivers/clk/rockchip/clk-rk3036.c | |
| parent | 9f11b885e133d1f400003323bedfa953c4247e95 (diff) | |
UPSTREAM: clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.
Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.7-clk/next
commit 0fda2be634398f4b8d53c0436311f99557e56c4e)
Conflicts:
drivers/clk/rockchip/clk-rk3228.c
[zx: there is no rk3228 clock controller, apply this patch for
clk-rk3366.]
Change-Id: I48fde9facccd41585873c997b0b02a7a73972717
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3036.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3036.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c index c289fdc3a17f..c9a53209333e 100644 --- a/drivers/clk/rockchip/clk-rk3036.c +++ b/drivers/clk/rockchip/clk-rk3036.c @@ -113,7 +113,10 @@ static const struct rockchip_cpuclk_reg_data rk3036_cpuclk_data = { .core_reg = RK2928_CLKSEL_CON(0), .div_core_shift = 0, .div_core_mask = 0x1f, + .mux_core_alt = 1, + .mux_core_main = 0, .mux_core_shift = 7, + .mux_core_mask = 0x1, }; PNAME(mux_pll_p) = { "xin24m", "xin24m" }; |