summaryrefslogtreecommitdiff
path: root/drivers/clk/rockchip/clk-px30.c
diff options
context:
space:
mode:
authorFinley Xiao <finley.xiao@rock-chips.com>2018-05-07 10:34:45 +0800
committerTao Huang <huangtao@rock-chips.com>2018-05-14 10:28:58 +0800
commitf422b3370a5b6fab78366e8472fc2d23da48ad86 (patch)
tree0f7ca5da7ff91d0e7537ccc1dce188f9c53ebc69 /drivers/clk/rockchip/clk-px30.c
parent9019a912ded0233a79196ec933df07e582ac6696 (diff)
clk: rockchip: px30: Set max parent rate for pdm fractional divider
Change-Id: I4a2fc90070d380fed280494784f46005f2b5b18d Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-px30.c')
-rw-r--r--drivers/clk/rockchip/clk-px30.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index ed35e3ea2aea..28248510dce8 100644
--- a/drivers/clk/rockchip/clk-px30.c
+++ b/drivers/clk/rockchip/clk-px30.c
@@ -22,6 +22,7 @@
#define PX30_GRF_SOC_STATUS0 0x480
#define PX30_I2S_FRAC_MAX_PRATE 600000000
+#define PX30_PDM_FRAC_MAX_PRATE 600000000
enum px30_plls {
apll, dpll, cpll, npll, apll_b_h, apll_b_l,
@@ -558,7 +559,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
PX30_CLKSEL_CON(27), 0,
PX30_CLKGATE_CON(9), 10, GFLAGS,
- &px30_pdm_fracmux, 0),
+ &px30_pdm_fracmux, PX30_PDM_FRAC_MAX_PRATE),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
PX30_CLKGATE_CON(9), 11, GFLAGS),