diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-08-15 15:36:16 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-08-22 09:31:20 +0800 |
| commit | bb1005b17c7b602b83a08b1ec047f396e655f7b2 (patch) | |
| tree | 6d3c6d1af3a5f9072a83abff8ac7809ed34f4bfa /drivers/clk/rockchip/clk-px30.c | |
| parent | c9ff227e0b7cf0ea1b2c50d363bc0af438c8e6ce (diff) | |
clk: rockchip: px30: Add support to set parent rate for vopl dclk
Change-Id: I208471f938b1795273c4f33ac35b82d667a2b312
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-px30.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-px30.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 58bc65c72423..9b340f5926cd 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -429,7 +429,7 @@ static struct rockchip_clk_branch px30_clk_branches[] __initdata = { &px30_dclk_vopb_fracmux, 0), GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT, PX30_CLKGATE_CON(2), 4, GFLAGS), - COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, 0, + COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, PX30_CLKSEL_CON(8), 11, 1, MFLAGS, 0, 8, DFLAGS, PX30_CLKGATE_CON(2), 6, GFLAGS), COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT, |