diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-06-20 10:09:34 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-08-29 09:16:25 +0800 |
| commit | 543172cfe30641ea9ab396b78e3331f9ba321342 (patch) | |
| tree | 66aeb07c8012c6b0c720c28126e3860e2e08a062 /drivers/clk/rockchip/clk-px30.c | |
| parent | 75c66d931afac703e213eddc2a65a2ae0b9ddda9 (diff) | |
clk: rockchip: Add support to get boost configure from devicetree
There are some configuration options for cpu boost, such as low
frequency, higt frequency, boost backup pll, and so on.
Change-Id: I35d65f05bbd5ef2a70e4a2e4637e7b4f9f67dda9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-px30.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-px30.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c index 9b340f5926cd..52a75e12f433 100644 --- a/drivers/clk/rockchip/clk-px30.c +++ b/drivers/clk/rockchip/clk-px30.c @@ -191,7 +191,7 @@ PNAME(mux_usbphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; PNAME(mux_mipidsiphy_ref_p) = { "xin24m", "clk_ref24m_pmu" }; static struct rockchip_pll_clock px30_pll_clks[] __initdata = { - [apll] = PLL_BOOST(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 0, PX30_PLL_CON(0), PX30_MODE_CON, 0, 0, 0, px30_pll_rates), [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, |