diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-06-20 14:37:55 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-06-20 16:12:26 +0800 |
| commit | 6a010ad23e37dda2ca8a221d78329a99286a21f3 (patch) | |
| tree | 9812391db33a1583bd127a331cb02629c8bd6774 /drivers/clk/rockchip/clk-pll.c | |
| parent | 0fac823c0e32cc74af40767f67e1e7eeffa35e0b (diff) | |
clk: rockchip: Fix rk3036 pll rate overflow calculation on 32-bit
Change-Id: I4e367893e97828b01b3e6ec457714c722d2c0af6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip/clk-pll.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index dea6ce39cb04..addcdb07553a 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -495,7 +495,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, { struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); struct rockchip_pll_rate_table cur; - u64 rate64 = prate; + u64 rate64 = prate, frac_rate64 = prate; if (pll->sel && pll->scaling) return pll->scaling; @@ -510,7 +510,7 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw, if (cur.dsmpd == 0) { /* fractional mode */ - u64 frac_rate64 = prate * cur.frac; + frac_rate64 *= cur.frac; do_div(frac_rate64, cur.refdiv); rate64 += frac_rate64 >> 24; |