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authorGavin Shan <shangw@linux.vnet.ibm.com>2013-11-12 14:49:21 +0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-11-29 11:28:08 -0800
commit80e6b610e7442644507d76a38a98e1ab68695ad6 (patch)
tree2e615af6f5ce6fee73eb6d7e888cfa0168ea4e5c /arch
parent3f0387f7a915418bc7df3d1861d8f3536f348244 (diff)
powerpc/eeh: Enable PCI_COMMAND_MASTER for PCI bridges
commit bf898ec5cbd33be11147743bee27b66b10cb2f85 upstream. On PHB3, we will fail to fetch IODA tables without PCI_COMMAND_MASTER on PCI bridges. According to one experiment I had, the MSIx interrupts didn't raise from the adapter without the bit applied to all upstream PCI bridges including root port of the adapter. The patch forces to have that bit enabled accordingly. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/kernel/eeh.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 55593ee2d5aa..c766cf575520 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -687,6 +687,15 @@ void eeh_save_bars(struct eeh_dev *edev)
for (i = 0; i < 16; i++)
eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
+
+ /*
+ * For PCI bridges including root port, we need enable bus
+ * master explicitly. Otherwise, it can't fetch IODA table
+ * entries correctly. So we cache the bit in advance so that
+ * we can restore it after reset, either PHB range or PE range.
+ */
+ if (edev->mode & EEH_DEV_BRIDGE)
+ edev->config_space[1] |= PCI_COMMAND_MASTER;
}
/**