diff options
| author | Weixin Zhou <zwx@rock-chips.com> | 2019-03-14 10:43:40 +0800 |
|---|---|---|
| committer | Weixin Zhou <zwx@rock-chips.com> | 2019-03-14 10:45:10 +0800 |
| commit | 747f81458287f7a857017b9fb41e7f6e577d9780 (patch) | |
| tree | dae0b2c3e1a91ed6db2af98d3f27940fd9d696d4 /arch/arm64/boot/dts | |
| parent | b2cc197cf7c9a36354a112d0cfa9cee17047c1a0 (diff) | |
arm64: dts: rockchip: rk3399pro-npu: add efuse node and info
Change-Id: I1242fc127da02dff5d0e02418c2a540d21983430
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi index 6663c7305d7b..2ca2a25c04ac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi @@ -52,6 +52,9 @@ compatible = "operating-points-v2"; opp-shared; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + opp-408000000 { opp-hz = /bits/ 64 <408000000>; opp-microvolt = <750000 750000 950000>; @@ -87,6 +90,12 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; + nvmem-cell-names = "id", "cpu-version"; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -321,6 +330,36 @@ }; }; + efuse: efuse@ff260000 { + compatible = "rockchip,rk1808-efuse"; + reg = <0x0 0xff3b0000 0x0 0x50>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_EFUSE_NS>, <&cru PCLK_EFUSE>; + clock-names = "sclk_efuse", "pclk_efuse"; + assigned-clocks = <&cru SCLK_EFUSE_NS>; + assigned-clock-rates = <24000000>; + rockchip,efuse-size = <0x20>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + logic_leakage: logic-leakage@18 { + reg = <0x18 0x1>; + }; + npu_leakage: npu-leakage@19 { + reg = <0x19 0x1>; + }; + efuse_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + }; + cru: clock-controller@ff350000 { compatible = "rockchip,rk1808-cru"; reg = <0x0 0xff350000 0x0 0x5000>; @@ -597,6 +636,9 @@ rockchip,pvtm-temp-prop = <(-20) (-26)>; rockchip,thermal-zone = "soc-thermal"; + nvmem-cells = <&npu_leakage>; + nvmem-cell-names = "leakage"; + opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <750000 750000 950000>; |