diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2018-10-09 11:53:44 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-10-09 14:59:04 +0800 |
| commit | 1c450a80824496dc9cf23c79044267fc53ee5706 (patch) | |
| tree | e25506daf5238c68dbcef1bf1155c055baade622 /arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi | |
| parent | c7f27e053c9f8b4094bac7786ef25920c96a8c55 (diff) | |
clk: rockchip: rk1808: rename SCLK_GPIO to DBCLK_GPIO
Change-Id: I1ed6fe175fb2e640a7a61e1a2e799e94e76b435f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi index 65bed2aad3f8..f8964c6c47ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi @@ -384,7 +384,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff4c0000 0x0 0x100>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_PMU_GPIO0>, <&cru PCLK_GPIO0_PMU>; + clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -396,7 +396,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff690000 0x0 0x100>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO1>, <&cru PCLK_GPIO1>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -408,7 +408,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff6a0000 0x0 0x100>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO2>, <&cru PCLK_GPIO2>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -420,7 +420,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff6b0000 0x0 0x100>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO3>, <&cru PCLK_GPIO3>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; @@ -432,7 +432,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff6c0000 0x0 0x100>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO4>, <&cru PCLK_GPIO4>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; |