diff options
| author | CanYang He <hcy@rock-chips.com> | 2018-04-26 14:01:51 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-04-26 16:35:05 +0800 |
| commit | f48d45778622b9f64eaac44b3f187b96f90d2192 (patch) | |
| tree | 1fd70ba4b0daae5e3f1d2c661fc7e6ec075288e6 /arch/arm64/boot/dts/rockchip/rk3399.dtsi | |
| parent | ff3dcfed5fa83dc1be2fee44213c282af02127aa (diff) | |
arm64: dts: rockchip: increase mcu frequency to 97mhz for rk3399
mcu run at 97MHz to reduce lpddr4 scale frequency elapsed time
Change-Id: Ie2805eaf0d902c9531819217d05a86775d85f809
Signed-off-by: CanYang He <hcy@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 527cb4c20dee..84f38ab45019 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1451,8 +1451,8 @@ reg = <0x0 0xff750000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&pmucru PLL_PPLL>; - assigned-clock-rates = <676000000>; + assigned-clocks = <&pmucru PLL_PPLL>, <&pmucru FCLK_CM0S_SRC_PMU>; + assigned-clock-rates = <676000000>, <97000000>; }; cru: clock-controller@ff760000 { |