diff options
| author | Hu Kejun <william.hu@rock-chips.com> | 2018-03-28 19:24:21 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-04-13 18:46:31 +0800 |
| commit | 53219cd8f38e71992c20210f694e6ef266a3ca7c (patch) | |
| tree | a8749f65eeb23b5003cfe33773d74b2215857662 /arch/arm64/boot/dts/rockchip/rk3399.dtsi | |
| parent | c05bc80b87ec5562e50f040ffbc7a8a91e2f0a05 (diff) | |
arm64: dts: rockchip: Add rkisp1 for rk3399
Change-Id: Ie0eb7088d08f9c0cbd0443b6f9c635ade9b4cc8f
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e5cd7c9e902c..32821b8e11b2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1558,6 +1558,16 @@ }; }; + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + status = "disabled"; + }; + pvtm: pvtm { compatible = "rockchip,rk3399-pvtm"; clocks = <&cru SCLK_PVTM_CORE_L>, @@ -1879,6 +1889,22 @@ status = "disabled"; }; + rkisp1_0: rkisp1@ff910000 { + compatible = "rockchip,rk3399-rkisp1"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, + <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "hclk_isp", + "aclk_isp_wrap", "hclk_isp_wrap"; + devfreq = <&dmc>; + power-domains = <&power RK3399_PD_ISP0>; + iommus = <&isp0_mmu>; + status = "disabled"; + }; + isp0_mmu: iommu@ff914000 { compatible = "rockchip,iommu"; reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; @@ -1892,6 +1918,22 @@ status = "disabled"; }; + rkisp1_1: rkisp1@ff920000 { + compatible = "rockchip,rk3399-rkisp1"; + reg = <0x0 0xff920000 0x0 0x4000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_ISP1>, + <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, + <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "hclk_isp", + "aclk_isp_wrap", "hclk_isp_wrap"; + devfreq = <&dmc>; + power-domains = <&power RK3399_PD_ISP1>; + iommus = <&isp1_mmu>; + status = "disabled"; + }; + isp1_mmu: iommu@ff924000 { compatible = "rockchip,iommu"; reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; |