diff options
| author | Hu Kejun <william.hu@rock-chips.com> | 2018-04-24 11:43:06 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-07-05 09:23:19 +0800 |
| commit | 230a1174bcfcd83659516d3e8440a7b942da9457 (patch) | |
| tree | 8f9d5403012595a0f5d2348306872d1e49f8d709 /arch/arm64/boot/dts/rockchip/rk3399.dtsi | |
| parent | be6abc01150d906580f469daf9007a36e99bc5b1 (diff) | |
arm64: dts: rockchip: add mipi_dphy_tx1rx1 and modify rkisp1_1 for rk3399
Change-Id: I94d01c6963dc5f2f9b61159df1b13fc0bb32a0f1
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 7e2f45515622..406056aad974 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1910,7 +1910,7 @@ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "isp0_mmu"; #iommu-cells = <0>; - clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; + clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399_PD_ISP0>; rk_iommu,disable_reset_quirk; @@ -1923,10 +1923,12 @@ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru SCLK_ISP1>, <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, - <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; + <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>, + <&cru PCLK_ISP1_WRAPPER>; clock-names = "clk_isp", "aclk_isp", "hclk_isp", - "aclk_isp_wrap", "hclk_isp_wrap"; + "aclk_isp_wrap", "hclk_isp_wrap", + "pclk_isp_wrap"; devfreq = <&dmc>; power-domains = <&power RK3399_PD_ISP1>; iommus = <&isp1_mmu>; @@ -1939,7 +1941,7 @@ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; interrupt-names = "isp1_mmu"; #iommu-cells = <0>; - clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; + clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; clock-names = "aclk", "hclk"; power-domains = <&power RK3399_PD_ISP1>; rk_iommu,disable_reset_quirk; @@ -2043,6 +2045,20 @@ }; }; + mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@0xff968000 { + compatible = "rockchip,rk3399-mipi-dphy"; + reg = <0x0 0xff968000 0x0 0x8000>; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru PCLK_VIO_GRF>, + <&cru PCLK_MIPI_DSI1>; + clock-names = "dphy-ref", "dphy-cfg", + "grf", "pclk_mipi_dsi"; + rockchip,grf = <&grf>; + power-domains = <&power RK3399_PD_VIO>; + status = "disabled"; + }; + edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; |