diff options
| author | Shawn Lin <shawn.lin@rock-chips.com> | 2017-10-23 09:09:19 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2017-10-23 15:10:04 +0800 |
| commit | a7e81131d2be792b628a24a40d1ee38991eea5e2 (patch) | |
| tree | 5d806079eb540fb879b62d62376c215e0dff10f9 /arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | |
| parent | 529190e011ced4a95a7eff627c8890fa10f24ac0 (diff) | |
arm64: dts: rockchip: remove assigning ref clock of PCIe for Sapphire board
Change-Id: I84c55f4b7d7c7394d511e3714e6021cafac55ec4
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 2b51a11ee04a..427915e3e209 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -505,9 +505,6 @@ }; &pcie0 { - assigned-clocks = <&cru SCLK_PCIEPHY_REF>; - assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; - assigned-clock-rates = <100000000>; ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; |