diff options
| author | Chaoqing Xu <shawn.xu@rock-chips.com> | 2019-02-25 17:59:45 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2019-02-26 15:00:07 +0800 |
| commit | 7229af9d0c03567c5b08ddbb104ee8b851b68e6a (patch) | |
| tree | 088e53d78e496623874a3fe4949751ce498d2a52 /arch/arm64/boot/dts/rockchip/rk3399-android.dtsi | |
| parent | af40bf26048513d87d7559314e7198ca6d6d82c7 (diff) | |
arm64: dts: rockchip: rk3399-android: fix clk_cif_pll use wrong clk
Change-Id: I66e04ede6b528a0b016171ab05363e8a74d9ec0b
Signed-off-by: Chaoqing Xu <shawn.xu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3399-android.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399-android.dtsi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi index a1ed5c23ed4a..95942d278058 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi @@ -170,8 +170,11 @@ compatible = "rockchip,rk3399-isp", "rockchip,isp"; reg = <0x0 0xff910000 0x0 0x4000>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru SCLK_CIF_OUT_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; + assigned-clock-rates = <800000000>; clocks = - <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>, <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>, @@ -212,7 +215,7 @@ <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>, <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>, - <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>, <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>; |