diff options
| author | WeiYong Bi <bivvy.bi@rock-chips.com> | 2017-07-17 10:58:32 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2017-07-28 09:23:13 +0800 |
| commit | e21df2959179efc289cee9c17a67e5bc9e3c157a (patch) | |
| tree | 3e0be31f5fba488810f0db982457777a8e473bea /arch/arm64/boot/dts/rockchip/rk3368.dtsi | |
| parent | 62fd23412357a855ad9d0d0e44e76dbc3707585b (diff) | |
arm64: dts: rockchip: rk3368: export MIPI DPHY PLL clock
Change-Id: I15ef0a01cde0459d1993110f5653f6bf10f99a64
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3368.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3368.dtsi | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 409722c6e278..167531b4cc6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -1426,8 +1426,8 @@ compatible = "rockchip,rk3368-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x4000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_MIPI_DSI0>; - clock-names = "pclk"; + clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>; + clock-names = "pclk", "hs_clk"; resets = <&cru SRST_MIPIDSI0>; reset-names = "apb"; phys = <&mipi_dphy>; @@ -1450,11 +1450,13 @@ mipi_dphy: mipi-dphy@ff968000 { compatible = "rockchip,rk3368-mipi-dphy"; reg = <0x0 0xff968000 0x0 0x4000>; - #phy-cells = <0>; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>; clock-names = "ref", "pclk"; + clock-output-names = "mipi_dphy_pll"; + #clock-cells = <0>; resets = <&cru SRST_MIPIDPHYTX>; reset-names = "apb"; + #phy-cells = <0>; status = "disabled"; }; |