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authorXu Jianqun <jay.xu@rock-chips.com>2017-05-10 09:21:04 +0800
committerXu Jianqun <jay.xu@rock-chips.com>2017-05-10 09:21:04 +0800
commit4d81e6715cf8da529095b85457c89742f266494c (patch)
tree3dd5ff7594ac872001e84997276c9462a3d47361 /arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
parentb9ca500f210b5d2998de89c24621cb07c0dc1915 (diff)
arm64: dts: rk3368-android: revert to use uart2 for debug
Change-Id: I5e6c88e185a2ad39b082ad4b989589cd46ecb874 Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3368-android.dtsi')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-android.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
index ac5e8fa1189f..8339cca08cb0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-android.dtsi
@@ -42,17 +42,17 @@
/ {
chosen {
- bootargs = "earlycon=uart8250,mmio32,0xff1b0000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
+ bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
};
fiq_debugger: fiq-debugger {
compatible = "rockchip,fiq-debugger";
- rockchip,serial-id = <3>;
+ rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
pinctrl-names = "default";
- pinctrl-0 = <&uart3_xfer>;
+ pinctrl-0 = <&uart2_xfer>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; /* signal irq */
};
@@ -179,7 +179,7 @@
};
};
-&uart3 {
+&uart2 {
status = "okay";
};