diff options
| author | Feng Xiao <xf@rock-chips.com> | 2016-03-14 18:01:44 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2016-03-22 19:30:16 +0800 |
| commit | 54ca0b112b92506535afb2d3459914f4b029f6a1 (patch) | |
| tree | 9b4252b1bc04626d8942a992e8c7513346d2808d /arch/arm64/boot/dts/rockchip/rk3366.dtsi | |
| parent | 4ed52a563349248e8832e28c526c95b0c0834702 (diff) | |
ARM64: dts: rk3366: assigned parents for clk_32k
Change-Id: I1742823658aa46226e3112969d3eabc695921fb5
Signed-off-by: Feng Xiao <xf@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3366.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3366.dtsi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi index 06e6ea0004ef..a9b6bc7551d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi @@ -662,6 +662,7 @@ #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = + <&cru SCLK_32K>, <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>, <&cru PLL_CPLL>, <&cru PLL_GPLL>, <&cru PLL_NPLL>, <&cru PLL_MPLL>, @@ -669,6 +670,7 @@ <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>, <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>; assigned-clock-rates = + <0>, <0>, <0>, <750000000>, <576000000>, <594000000>, <594000000>, @@ -676,6 +678,7 @@ <375000000>, <288000000>, <100000000>, <100000000>; assigned-clock-parents = + <&cru SCLK_32K_INTR>, <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>; }; |