diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2016-04-21 19:56:37 +0800 |
|---|---|---|
| committer | Finley Xiao <finley.xiao@rock-chips.com> | 2016-04-21 19:56:37 +0800 |
| commit | 460024031667bd7bac235a7824c2f630d52e5022 (patch) | |
| tree | 56b47700fa017281d9eb1f690a125c6934ed6994 /arch/arm64/boot/dts/rockchip/rk3366.dtsi | |
| parent | 4a4215ae1264cbd54bf1f448ff63be67bc3273eb (diff) | |
ARM64: dts: rockchip: rk3366: assign parent for gpu and wifi.
Gpu's 480MHz need to select usbphy_480m as parent.
The jitter will be lower, if sclk_wifidsp is supplied by pll_wifi.
Change-Id: I13e5077d55ab80e5224bac36b469e39d556bd347
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3366.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3366.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi index 6b8096cccbd3..75784150d756 100644 --- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi @@ -683,7 +683,7 @@ #clock-cells = <1>; #reset-cells = <1>; assigned-clocks = - <&cru SCLK_32K>, + <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>, <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>, <&cru PLL_CPLL>, <&cru PLL_GPLL>, <&cru PLL_NPLL>, <&cru PLL_MPLL>, @@ -693,7 +693,7 @@ <&cru ACLK_BUS>, <&cru ACLK_PERI0>, <&cru ACLK_PERI1>; assigned-clock-rates = - <0>, + <0>, <0>, <0>, <0>, <750000000>, <576000000>, <594000000>, <594000000>, @@ -703,7 +703,7 @@ <288000000>, <288000000>, <144000000>; assigned-clock-parents = - <&cru SCLK_32K_INTR>, + <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>, <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>; }; |