diff options
| author | Xiao Yao <xiaoyao@rock-chips.com> | 2018-02-28 17:46:49 +0800 |
|---|---|---|
| committer | Xiao Yao <xiaoyao@rock-chips.com> | 2018-02-28 17:46:49 +0800 |
| commit | edda3bd7f27aaec1fabca476d44d22a8ee339312 (patch) | |
| tree | a505d3865417dc235614df76319609acc6a52748 /arch/arm64/boot/dts/rockchip/rk3328.dtsi | |
| parent | d23a54bc04475cbc0739431aea743db19bc78ec7 (diff) | |
arm64: dts: rockchip: add sample/drv clk for sdmmc/ext for rk3328 chip
Change-Id: I2c00f2e461e283abbc18b426f5298490dee4bdfe
Signed-off-by: Xiao Yao <xiaoyao@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3328.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3328.dtsi | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 88bf1e078914..2e883ed8f46e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -1208,8 +1208,9 @@ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff500000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1326,8 +1327,9 @@ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff5f0000 0x0 0x4000>; clock-freq-min-max = <400000 150000000>; - clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>; - clock-names = "biu", "ciu"; + clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, + <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; |