diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-06-21 18:45:42 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-06-25 09:34:41 +0800 |
| commit | ba98e189b68be0fe123deb04ebe669d3948f8f61 (patch) | |
| tree | 2b5cb726da33df13b7188373ad6eb522f661459c /arch/arm64/boot/dts/rockchip/rk3326.dtsi | |
| parent | 403e528a2230afe6e0c0b738ab74f35f2f55112c (diff) | |
arm64: dts: rockchip: px30: Change armclk rate to 600MHz
The initial voltage may be too low for 816MHz and it is enough for
600MHz. And as the alternate pll clock of armclk is created when
pmucru driver initialize, so move ARMCLK to pmucru node.
Change-Id: I1f443d55c74e5212a19e42e08b54ec946b4692d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3326.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3326.dtsi | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3326.dtsi b/arch/arm64/boot/dts/rockchip/rk3326.dtsi index e0a59f32aeb2..89661162d4dc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3326.dtsi @@ -7,10 +7,8 @@ #include "px30.dtsi" &cru { - assigned-clocks = - <&cru PLL_NPLL>, <&cru ARMCLK>; - assigned-clock-rates = - <1040000000>, <816000000>; + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1040000000>; }; &gpu_opp_table { |