diff options
| author | Wyon Bi <bivvy.bi@rock-chips.com> | 2018-10-10 11:22:36 +0800 |
|---|---|---|
| committer | Wyon Bi <bivvy.bi@rock-chips.com> | 2018-12-29 16:41:15 +0800 |
| commit | 4fadd4c39c436c6d117d0bdc7e77e64579463e0b (patch) | |
| tree | fc9a685599ba22874bb4b1cf0786cf6edb03fee7 /arch/arm64/boot/dts/rockchip/rk3326.dtsi | |
| parent | 1521458687e4edcfd844bce9ef8c62ab0d165fa8 (diff) | |
arm64: dts: rockchip: px30: Add support for video phy
Change-Id: Icfc90340972646a58b0ff6137a63d474d1171191
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk3326.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3326.dtsi | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3326.dtsi b/arch/arm64/boot/dts/rockchip/rk3326.dtsi index 314376b6990f..bb9db4dc5e2b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3326.dtsi @@ -21,3 +21,59 @@ opp-microvolt-L3 = <1050000>; }; }; + +&rgb { + phys = <&video_phy>; + phy-names = "phy"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_m1_rgb_pins>; + pinctrl-1 = <&lcdc_m1_sleep_pins>; +}; + +&pinctrl { + lcdc { + lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ + <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ + <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ + <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ + <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ + <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ + <3 RK_PC0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ + <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ + <3 RK_PC2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ + <3 RK_PC3 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ + <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ + <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ + <3 RK_PC6 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ + <3 RK_PC7 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ + <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ + <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ + <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ + <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ + }; + + lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ + }; + }; +}; |