diff options
| author | Sugar Zhang <sugar.zhang@rock-chips.com> | 2018-09-23 23:04:25 +0800 |
|---|---|---|
| committer | Sugar Zhang <sugar.zhang@rock-chips.com> | 2018-09-26 14:54:45 +0800 |
| commit | f8df3865b817b7a7a82df0865e03ab5b36d6bfc7 (patch) | |
| tree | 47d77bc3e7e873cff8c77dec036f0d35be6f142b /arch/arm64/boot/dts/rockchip/rk1808.dtsi | |
| parent | 068c68fe346b19bf15f0d3a406b826b428ad8216 (diff) | |
arm64: dts: rockchip: add i2s-tdm, i2s, pdm, vad for rk1808
Change-Id: I13d6da81713704d3ee53e12d801882eeef6d5e64
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk1808.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk1808.dtsi | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index e8ed14bdfbfc..a9f7ff8d8b6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -841,6 +841,83 @@ status = "disabled"; }; + i2s0: i2s@ff7e0000 { + compatible = "rockchip,rk1808-i2s-tdm"; + reg = <0x0 0xff7e0000 0x0 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac 16>, <&dmac 17>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_sclktx + &i2s0_8ch_sclkrx + &i2s0_8ch_lrcktx + &i2s0_8ch_lrckrx + &i2s0_8ch_sdi0 + &i2s0_8ch_sdi1 + &i2s0_8ch_sdi2 + &i2s0_8ch_sdi3 + &i2s0_8ch_sdo0 + &i2s0_8ch_sdo1 + &i2s0_8ch_sdo2 + &i2s0_8ch_sdo3 + &i2s0_8ch_mclk>; + status = "disabled"; + }; + + i2s1: i2s@ff7f0000 { + compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff7f0000 0x0 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 18>, <&dmac 19>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_sclk + &i2s1_2ch_lrck + &i2s1_2ch_sdi + &i2s1_2ch_sdo>; + status = "disabled"; + }; + + pdm: pdm@ff800000 { + compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; + reg = <0x0 0xff800000 0x0 0x1000>; + clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 24>; + dma-names = "rx"; + resets = <&cru SRST_PDM>; + reset-names = "pdm-m"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_clk + &pdm_clk1 + &pdm_sdi0 + &pdm_sdi1 + &pdm_sdi2 + &pdm_sdi3>; + status = "disabled"; + }; + + vad: vad@ff810000 { + compatible = "rockchip,rk1808-vad"; + /* vad buf: last 256 KB system sram */ + reg = <0x0 0xff810000 0x0 0x10000>, <0x0 0xfedc0000 0x0 0x40000>; + reg-names = "vad", "vad-memory"; + clocks = <&cru HCLK_VAD>; + clock-names = "hclk"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <1>; + status = "disabled"; + }; + csi_tx: csi@ffb20000 { compatible = "rockchip,rk1808-mipi-csi"; reg = <0x0 0xffb20000 0x0 0x500>; |