diff options
| author | William Wu <william.wu@rock-chips.com> | 2018-10-23 15:06:04 +0800 |
|---|---|---|
| committer | William Wu <william.wu@rock-chips.com> | 2018-10-23 16:49:32 +0800 |
| commit | f561f2cf86b5cef349e8f991b9aaced5a1cb8d39 (patch) | |
| tree | 6629f36b3573d62a0f268da3a8fde4b788481e54 /arch/arm64/boot/dts/rockchip/rk1808.dtsi | |
| parent | 9ce38fd918bf14c81950fb13392a31073e913979 (diff) | |
arm64: dts: rockchip: enable power domain for rk1808 dwc3
Change-Id: Ia18a03b3c68b560ee4c5e47a4a82f11b786c8964
Signed-off-by: William Wu <william.wu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk1808.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk1808.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index 5700d18033c0..52d6c3eccc6c 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -143,6 +143,7 @@ "suspend_clk"; assigned-clocks = <&cru SCLK_USB3_OTG0_SUSPEND>; assigned-clock-rates = <24000000>; + power-domains = <&power RK1808_PD_PCIE>; #address-cells = <2>; #size-cells = <2>; ranges; |