diff options
| author | Shixiang Zheng <shixiang.zheng@rock-chips.com> | 2018-10-11 21:30:12 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-10-12 19:01:41 +0800 |
| commit | d1df8bb20e3cc818b2cc2d0398073b232234b274 (patch) | |
| tree | 1a5626d0827f099f6dd8b138decfebd40eef437e /arch/arm64/boot/dts/rockchip/rk1808.dtsi | |
| parent | e919ced3e4467ab2b588e608db705c4035b2123e (diff) | |
arm64: dts: rockchip: add rga node for rk1808
Change-Id: I526781fc6716276ad0500e8d7615361f77dc031a
Signed-off-by: Shixiang Zheng <shixiang.zheng@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk1808.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk1808.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index d3e825232467..673ae5b41fe7 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -975,6 +975,18 @@ status = "disabled"; }; + rk_rga: rk_rga@ffaf0000 { + compatible = "rockchip,rga2"; + dev_mode = <0>; + reg = <0x0 0xffaf0000 0x0 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK1808_PD_VIO>; + dma-coherent; + status = "disabled"; + }; + vop_lite: vop@ffb00000 { compatible = "rockchip,rk1808-vop-lit"; reg = <0x0 0xffb00000 0x0 0x200>; |