diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-09-28 10:42:18 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-10-10 10:46:50 +0800 |
| commit | 701dfebbed7591d1f01168cfdffd73b91a3cb178 (patch) | |
| tree | 82383f12a7c408f4b551d1d24b229d15eb0a5c5d /arch/arm64/boot/dts/rockchip/rk1808.dtsi | |
| parent | 0b9b266a6c2f0f5cbf83fb37f68678dc381fab63 (diff) | |
arm64: dts: rockchip: rk1808: Add opp table for cpu
Change-Id: Ie9d683c59d61a83cb1e5e7df73e56bedffa56cfd
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk1808.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk1808.dtsi | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index b89b2603aba7..8684a5e2832b 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -45,6 +45,7 @@ reg = <0x0 0x0>; enable-method = "psci"; clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { @@ -53,6 +54,39 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; }; }; |