arm64: dts: rockchip: add usb nodes for rk1808

Add usb 2.0 host controller nodes, usb 3.0 otg controller
node, and usb 2.0 phy nodes for rk1808 SoC.

Change-Id: Icb23e3d1b929091b62824bba6f41ffb4ab262f69
Signed-off-by: William Wu <william.wu@rock-chips.com>

1 files changed, 89 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
index dacc05010535..fb0aba9d4ebc 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
@@ -82,6 +82,34 @@
 		#clock-cells = <0>;
 	};
 
+	usbdrd3: usb@fd000000 {
+		compatible = "rockchip,rk1808-dwc3";
+		clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>,
+			 <&cru SCLK_USB3_OTG0_SUSPEND>;
+		clock-names = "ref_clk", "bus_clk",
+			      "suspend_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3: dwc3@fd000000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfd000000 0x0 0x200000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			phys = <&u2phy_otg>;
+			phy-names = "usb2-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,tx-ipgap-linecheck-dis-quirk;
+			status = "disabled";
+		};
+	};
+
 	grf: syscon@fe000000 {
 		compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xfe000000 0x0 0x1000>;
@@ -89,6 +117,43 @@
 		#size-cells = <1>;
 	};
 
+	usb2phy_grf: syscon@fe010000 {
+		compatible = "rockchip,rk1808-usb2phy-grf", "syscon",
+			     "simple-mfd";
+		reg = <0x0 0xfe010000 0x0 0x8000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		u2phy: usb2-phy@100 {
+			compatible = "rockchip,rk1808-usb2phy";
+			reg = <0x100 0x10>;
+			clocks = <&cru SCLK_USBPHY_REF>;
+			clock-names = "phyclk";
+			#clock-cells = <0>;
+			assigned-clocks = <&cru USB480M>;
+			assigned-clock-parents = <&u2phy>;
+			clock-output-names = "usb480m_phy";
+			status = "disabled";
+
+			u2phy_host: host-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "linestate";
+				status = "disabled";
+			};
+
+			u2phy_otg: otg-port {
+				#phy-cells = <0>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-bvalid", "otg-id",
+						  "linestate";
+				status = "disabled";
+			};
+		};
+	};
+
 	pmugrf: syscon@fe410000 {
 		compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd";
 		reg = <0x0 0xfe410000 0x0 0x1000>;
@@ -575,6 +640,30 @@
 		status = "disabled";
 	};
 
+	usb_host0_ehci: usb@ffd80000 {
+		compatible = "generic-ehci";
+		reg = <0x0 0xffd80000 0x0 0x10000>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>,
+			 <&u2phy>;
+		clock-names = "usbhost", "arbiter", "utmi";
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb_host0_ohci: usb@ffd90000 {
+		compatible = "generic-ohci";
+		reg = <0x0 0xffd90000 0x0 0x10000>;
+		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>,
+			 <&u2phy>;
+		clock-names = "usbhost", "arbiter", "utmi";
+		phys = <&u2phy_host>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
 	gmac: ethernet@ffdd0000 {
 		compatible = "rockchip,rk1808-gmac";
 		reg = <0x0 0xffdd0000 0x0 0x10000>;