diff options
| author | Ziyuan Xu <xzy.xu@rock-chips.com> | 2018-10-09 10:15:48 +0800 |
|---|---|---|
| committer | Ziyuan Xu <xzy.xu@rock-chips.com> | 2018-10-09 10:21:59 +0800 |
| commit | 472f9736a6ac073b1601d3430e536542788c5bb9 (patch) | |
| tree | b7b203118d1d9b2bcb6a51be5a11d7376122cbde /arch/arm64/boot/dts/rockchip/rk1808.dtsi | |
| parent | b4a27215c5787d7a247e126c5e496aa6edf2843d (diff) | |
arm64: dts: rockchip: rk1808: change the clock resource index
The pinctrl-rockchip driver get the clock resource by of_clk_get
within the index 0 which requires the index of pclk_gpio should
be fixed to 0.
Change-Id: I619f12cb53002996d96f142c8889852be75c61e7
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk1808.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk1808.dtsi | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi index 099c00c03d71..80a79e91cc3c 100644 --- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi @@ -1165,7 +1165,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff4c0000 0x0 0x100>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_PMU_GPIO0>, <&cru PCLK_GPIO0_PMU>; + clocks = <&cru PCLK_GPIO0_PMU>, <&cru SCLK_PMU_GPIO0>; gpio-controller; #gpio-cells = <2>; @@ -1177,7 +1177,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff690000 0x0 0x100>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO1>, <&cru PCLK_GPIO1>; + clocks = <&cru PCLK_GPIO1>, <&cru SCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; @@ -1189,7 +1189,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff6a0000 0x0 0x100>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO2>, <&cru PCLK_GPIO2>; + clocks = <&cru PCLK_GPIO2>, <&cru SCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; @@ -1201,7 +1201,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff6b0000 0x0 0x100>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO3>, <&cru PCLK_GPIO3>; + clocks = <&cru PCLK_GPIO3>, <&cru SCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; @@ -1213,7 +1213,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff6c0000 0x0 0x100>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_GPIO4>, <&cru PCLK_GPIO4>; + clocks = <&cru PCLK_GPIO4>, <&cru SCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; |