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authorJianqun Xu <jay.xu@rock-chips.com>2018-10-06 16:12:16 +0800
committerTao Huang <huangtao@rock-chips.com>2018-10-06 16:21:03 +0800
commitfefd0db56d2458886a43765bda59256b36e64c59 (patch)
treeae9de4911f1b264ed4429abdfcb04e494b6ec25b /arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
parent20929b39afbf7bbce5ff42382b4a1481938dcdf2 (diff)
arm64: dts: rockchip: rk1808-evb: fix irqid of fiq-debugger
Change-Id: Ie473f821bf68483ba4a182db717e65a9970b40a9 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi')
-rw-r--r--arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
index 89b142a659e1..922428b56025 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808-evb.dtsi
@@ -94,7 +94,7 @@
/* If enable uart uses irq instead of fiq */
rockchip,irq-mode-enable = <0>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "okay";