diff options
| author | Cai YiWei <cyw@rock-chips.com> | 2018-07-16 16:46:32 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-07-23 14:44:26 +0800 |
| commit | b4539c7dad89c7f7a3058d73fc5fd9ae6a329709 (patch) | |
| tree | b757425a4834f617f2fb5a79d960d36cb00eb2b3 /arch/arm64/boot/dts/rockchip/px30.dtsi | |
| parent | 3d0829271918b3646d5f152b0c312beef1c687ed (diff) | |
ARM64: dts: rockchip: add a new cif node for px30
Change-Id: Ibfe9412ebaaede23168c1afe0104fad32a9d7882
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 3f85e8abc4ed..6d72cb4f3ca8 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1515,6 +1515,19 @@ status = "disabled"; }; + cif_new: cif-new@ff490000 { + compatible = "rockchip,px30-cif"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; + clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out"; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; + power-domains = <&power PX30_PD_VI>; + iommus = <&vip_mmu>; + status = "disabled"; + }; + vip_mmu: iommu@ff490800{ compatible = "rockchip,iommu"; reg = <0x0 0xff490800 0x0 0x100>; |