diff options
| author | Hu Kejun <william.hu@rock-chips.com> | 2018-12-12 17:34:08 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-12-14 17:12:40 +0800 |
| commit | 89212f02e21a189f82700bc49a001055978a0655 (patch) | |
| tree | 1010331a3009467777a205a2123d459d4e000762 /arch/arm64/boot/dts/rockchip/px30.dtsi | |
| parent | 993dd376b81f0fa5b41512302104c570294898f3 (diff) | |
arm64: dts: rockchip: px30: add mi/mipi irq setting
Change-Id: I2146d37c18d8418b32cf13736ecccb0510a851d9
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 0278326418b0..4ffe567cd762 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1619,7 +1619,10 @@ rkisp1: rkisp1@ff4a0000 { compatible = "rockchip,rk3326-rkisp1"; reg = <0x0 0xff4a0000 0x0 0x8000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru PCLK_ISP>; clock-names = "aclk_isp", "hclk_isp", |