diff options
| author | Finley Xiao <finley.xiao@rock-chips.com> | 2018-08-15 10:25:27 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-08-22 09:31:20 +0800 |
| commit | 79cf34e7324aaf2411e1a0d4c9cbd58047da7cce (patch) | |
| tree | c071e3de651f6b72a63668e56d55d8f653695c25 /arch/arm64/boot/dts/rockchip/px30.dtsi | |
| parent | ab350b549ae0f45e0842a56c5d71f1437451571d (diff) | |
arm64: dts: rockchip: Remove initial rate of npll for px30
As npll rate may be changed when enable vopl in uboot, so we can't
change npll rate in kernel on px30.
Change-Id: If62da5bb77cdd411a550b2dc6250d654134474e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 12b302a2c360..c67d27b94728 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1008,9 +1008,6 @@ rockchip,boost = <&cpu_boost>; #clock-cells = <1>; #reset-cells = <1>; - - assigned-clocks = <&cru PLL_NPLL>; - assigned-clock-rates = <1188000000>; }; cpu_boost: cpu-boost@ff2b8000 { |