diff options
| author | Hu Kejun <william.hu@rock-chips.com> | 2018-04-09 16:15:12 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-04-11 18:30:37 +0800 |
| commit | 064b747bf0abc7ceb4da11815d4fbfe521df72e6 (patch) | |
| tree | 9194847c49e05efc93f65bfd952974f02c858311 /arch/arm64/boot/dts/rockchip/px30.dtsi | |
| parent | 87dfc62bcb2c4fcd69ddff00b3246814029ed2af (diff) | |
arm64: dts: rockchip: add dts of rkisp1 for rk3326
Change-Id: I0e6fe49d8560aee7404e9685f9356978b7148c7a
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index d1cf8b73d507..61f2110a9b9d 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1007,6 +1007,16 @@ }; }; + mipi_dphy_rx0: mipi-dphy-rx0@ff2f0000 { + compatible = "rockchip,rk3326-mipi-dphy"; + reg = <0x0 0xff2f0000 0x0 0x4000>; + clocks = <&cru PCLK_MIPICSIPHY>; + clock-names = "dphy-ref"; + power-domains = <&power PX30_PD_VI>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + usb20_otg: usb@ff300000 { compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2"; @@ -1431,6 +1441,20 @@ status = "disabled"; }; + rkisp1: rkisp1@ff4a0000 { + compatible = "rockchip,rk3326-rkisp1"; + reg = <0x0 0xff4a0000 0x0 0x8000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru SCLK_ISP>, <&cru PCLK_ISP>; + clock-names = "aclk_isp", "hclk_isp", + "clk_isp", "pclk_isp"; + devfreq = <&dmc>; + power-domains = <&power PX30_PD_VI>; + iommus = <&isp_mmu>; + status = "disabled"; + }; + isp_mmu: iommu@ff4a8000 { compatible = "rockchip,iommu"; reg = <0x0 0xff4a8000 0x0 0x100>; |