diff options
| author | Zhong Yichong <zyc@rock-chips.com> | 2018-02-09 16:12:20 +0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2018-02-10 16:07:19 +0800 |
| commit | 16bb8bd923d10b70b442a769267b56daa6264f89 (patch) | |
| tree | 9f9fde66dd92b146ca18cf6cd2d0752424cab64b /arch/arm64/boot/dts/rockchip/px30.dtsi | |
| parent | 69441faf9e83bc1ef97e49696f32d6808c868b57 (diff) | |
arm64: dts: rockchip: px30: modify the isp reg range
Change-Id: I3326908e0445c1230b73169b9d9b34a31658d0b2
Signed-off-by: Zhong Yichong <zyc@rock-chips.com>
Diffstat (limited to 'arch/arm64/boot/dts/rockchip/px30.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/px30.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 67c7bc29f812..15c6eda185db 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1217,7 +1217,7 @@ rk_isp: rk_isp@ff4a0000 { compatible = "rockchip,px30-isp", "rockchip,isp"; - reg = <0x0 0xff4a0000 0x0 0x4000>; + reg = <0x0 0xff4a0000 0x0 0x8000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; |