diff options
| author | Wyon Bi <bivvy.bi@rock-chips.com> | 2017-10-18 09:11:37 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2017-10-19 14:30:16 +0800 |
| commit | ae8c318d1a91a7921e122700e086196f58cbc73b (patch) | |
| tree | 4f30c7e3852e97f87ff113120306fde2dc2019e3 /arch/arm/boot/dts/rk312x.dtsi | |
| parent | 76d1216b2c1a2128d3aa106db4db9485a3393bb4 (diff) | |
ARM: dts: rockchip: rk312x: add support for dsi
Change-Id: Id77c3496b8548ea5bd0b9e6c9b32de7199494484
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Diffstat (limited to 'arch/arm/boot/dts/rk312x.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk312x.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi index ec865cbb8107..52c77bcd09f0 100644 --- a/arch/arm/boot/dts/rk312x.dtsi +++ b/arch/arm/boot/dts/rk312x.dtsi @@ -308,6 +308,11 @@ #address-cells = <1>; #size-cells = <0>; + vop_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_vop>; + }; + vop_out_lvds: endpoint@1 { reg = <1>; remote-endpoint = <&lvds_in_vop>; @@ -326,6 +331,30 @@ status = "disabled"; }; + dsi: dsi@10110000 { + compatible = "rockchip,rk3128-mipi-dsi"; + reg = <0x10110000 0x4000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MIPI>, <&mipi_dphy>; + clock-names = "pclk", "hs_clk"; + resets = <&cru SRST_VIO_MIPI_DSI>; + reset-names = "apb"; + phys = <&mipi_dphy>; + phy-names = "mipi_dphy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + port { + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + }; + }; + gic: interrupt-controller@10139000 { compatible = "arm,cortex-a7-gic"; interrupt-controller; @@ -477,6 +506,19 @@ }; }; + mipi_dphy: mipi-dphy@20038000 { + compatible = "rockchip,rk3128-mipi-dphy"; + reg = <0x20038000 0x4000>; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>, <&cru HCLK_VIO_H2P>; + clock-names = "ref", "pclk", "h2p"; + clock-output-names = "mipi_dphy_pll"; + #clock-cells = <0>; + resets = <&cru SRST_MIPIPHY_P>; + reset-names = "apb"; + #phy-cells = <0>; + status = "disabled"; + }; + lvds: lvds@20038000 { compatible = "rockchip,rk3126-lvds"; reg = <0x20038000 0x4000>, <0x10110000 0x100>; |