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author | Sugar Zhang <sugar.zhang@rock-chips.com> | 2018-09-29 17:23:31 +0800 |
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committer | Tao Huang <huangtao@rock-chips.com> | 2018-12-17 14:38:47 +0800 |
commit | b4f93f7e7b52f9086f6b3643d0d145799d40bff6 (patch) | |
tree | 9049e4111006a7186100b1deabe19ed8da6d6cd4 /Documentation | |
parent | dae1e6294f32aa5ac7ea82c62631fb583990d8c9 (diff) |
clk: rockchip: add clock controller for rv1108
This patch add the clock tree definition for rv1108.
Change-Id: I9b55cd46c62331057fe8a404c606fe9d08f03388
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt new file mode 100644 index 000000000000..161326a4f9c1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt @@ -0,0 +1,59 @@ +* Rockchip RV1108 Clock and Reset Unit + +The RV1108 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rv1108-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_vip" - external VIP clock - optional + - "ext_i2s" - external I2S clock - optional + - "ext_gmac" - external GMAC clock - optional + - "hdmiphy" - external clock input derived from HDMI PHY - optional + - "usbphy" - external clock input derived from USB PHY - optional + +Example: Clock controller node: + + cru: cru@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial@10230000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10230000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + }; |