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| author | Wu Liang feng <wulf@rock-chips.com> | 2016-08-10 11:17:40 +0800 |
|---|---|---|
| committer | Huang, Tao <huangtao@rock-chips.com> | 2016-08-16 20:48:19 +0800 |
| commit | c72a0f978042b0f4cea95fa6a5895754885d6342 (patch) | |
| tree | 731ccd9ad37a0533282fa4085f467fd81d6705ca /Documentation | |
| parent | 86e6380a5b0dba3fb11c93b3a4347c44efb3ede0 (diff) | |
Revert "usb: dwc3: add dis_del_phy_power_chg_quirk"
This reverts commit ffee25e68d518aed3a505543355bff1d961159ff.
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/usb/dwc3.txt | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 8de381a44708..f1806c4f21e8 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -43,8 +43,6 @@ Optional properties: - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 PHY doesn't provide a free-running PHY clock. - - snps,dis_del_phy_power_chg_quirk: when set core will change PHY power - from P0 to P1/P2/P3 without delay. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold |