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authorElaine Zhang <zhangqing@rock-chips.com>2017-05-02 15:34:06 +0800
committerHeiko Stuebner <heiko@sntech.de>2017-06-02 15:57:32 +0200
commit223c24be740d293519ef8e03f5c075fab5512fd2 (patch)
tree1c6ec1a5a2eda821901245977d39c8ce775db50e
parent55bb6a633c33caf68ab470907ecf945289cb733d (diff)
clk: rockchip: mark some special clk as critical on rk3368v4.13-rockchip-clk1
The jtag clk no driver to handle them. But this clk need enable,so make it as critical. The ddrphy/ddrupctl clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--drivers/clk/rockchip/clk-rk3368.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 024762d3214d..fc56565379dd 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -638,7 +638,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
RK3368_CLKGATE_CON(7), 5, GFLAGS),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
@@ -861,6 +861,9 @@ static const char *const rk3368_critical_clocks[] __initconst = {
"pclk_pd_alive",
"pclk_peri",
"hclk_peri",
+ "pclk_ddrphy",
+ "pclk_ddrupctl",
+ "pmu_hclk_otg0",
};
static void __init rk3368_clk_init(struct device_node *np)