diff options
| author | Nickey Yang <nickey.yang@rock-chips.com> | 2017-09-18 17:05:37 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-09-19 19:25:10 +0200 |
| commit | bb4e6ff01ac356f82327d980e45fee8a65491328 (patch) | |
| tree | 47dceef62f8f8fd2ae3777a1b76674f04a99bcaa | |
| parent | 6354a06cbaa8c49d8377a6cee3e7db399c23601c (diff) | |
arm64: dts: rockchip: Correct MIPI DPHY PLL clock on rk3399
There is a further gate in between the mipidphy reference clock and the
actual ref-clock input to the dsi host, making the clock hirarchy look like
clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll
Fix the clock reference so that the whole clock subtree gets enabled when
the dsi host needs it.
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
[amended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3265b9..6aa43fd47148 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1629,7 +1629,7 @@ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; power-domains = <&power RK3399_PD_VIO>; |