diff options
| author | Elaine Zhang <zhangqing@rock-chips.com> | 2017-02-22 10:59:55 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-03-22 18:33:22 +0100 |
| commit | 9be83448951a404a6fd5cf43ee0245a9bccc02c1 (patch) | |
| tree | 55e43d2247420504b778f0a29635fd832e915221 | |
| parent | 7e2a9035c1dbc4632f1897a8fe580fc90f33c013 (diff) | |
clk: rockchip: add pll_wait_lock for pll_enablev4.12-rockchip-clk1
If pll is power down,when power up pll need wait pll lock.
The reference documents section:
PLL frequency change and lock check
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index eec51893a7e6..dd0433d4753e 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -269,6 +269,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw) writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), pll->reg_base + RK3036_PLLCON(1)); + rockchip_pll_wait_lock(pll); return 0; } @@ -501,6 +502,7 @@ static int rockchip_rk3066_pll_enable(struct clk_hw *hw) writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), pll->reg_base + RK3066_PLLCON(3)); + rockchip_pll_wait_lock(pll); return 0; } @@ -746,6 +748,7 @@ static int rockchip_rk3399_pll_enable(struct clk_hw *hw) writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), pll->reg_base + RK3399_PLLCON(3)); + rockchip_rk3399_pll_wait_lock(pll); return 0; } |