diff options
| author | Shawn Lin <shawn.lin@rock-chips.com> | 2016-12-16 17:42:37 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-01-13 12:03:55 +0100 |
| commit | 59cf70be5b7c6e3370f669976e3778104f4327ca (patch) | |
| tree | 2a5b232a43dd24865dd74802f874c1d970c693b7 | |
| parent | 712fa1777207c2f2703a6eb618a9699099cbe37b (diff) | |
arm64: dts: rockchip: add aspm-no-l0s for rk3399
Per the discussion of bug fix[1], we now actually
leaves the default clock choice for pcie phy is
derived from 24MHz OSC to guarantee the least BER.
So let's add aspm-no-l0s here and folks could delete
this property from their dts.
[1] https://patchwork.kernel.org/patch/9470519/
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 92b731f592c6..a28b51ce4232 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -283,6 +283,7 @@ #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; + aspm-no-l0s; bus-range = <0x0 0x1>; clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; |