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authorLuis R. Rodriguez <lrodriguez@atheros.com>2010-08-30 19:26:33 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2010-09-20 13:03:20 -0700
commitd14a2c2005c205bcd6742cac79dacd69436603b6 (patch)
treed423b43ea1a961fa293af5b64d314d226daac059
parentd0d3c686c7cb5a1b4d75df7fd76cae0d80f657a4 (diff)
ath9k_hw: fix parsing of HT40 5 GHz CTLs
commit 904879748d7439a6dabdc6be9aad983e216b027d upstream. The 5 GHz CTL indexes were not being read for all hardware devices due to the masking out through the CTL_MODE_M mask being one bit too short. Without this the calibrated regulatory maximum values were not being picked up when devices operate on 5 GHz in HT40 mode. The final output power used for Atheros devices is the minimum between the calibrated CTL values and what CRDA provides. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 8ccf3742423f..e4babfbe49aa 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -554,7 +554,7 @@ enum ath9k_cipher {
#define SD_NO_CTL 0xE0
#define NO_CTL 0xff
-#define CTL_MODE_M 7
+#define CTL_MODE_M 0xf
#define CTL_11A 0
#define CTL_11B 1
#define CTL_11G 2