diff options
| author | Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> | 2019-05-22 16:09:22 +0200 |
|---|---|---|
| committer | Christoph Muellner <christoph.muellner@theobroma-systems.com> | 2019-10-02 00:39:43 +0200 |
| commit | fb38758995556d62972124eeb9cc81d69e48f68d (patch) | |
| tree | bb7230fcb944a1111f66cec28c5607cf754139fb | |
| parent | bcb54adcef56724e483826573d9298875138c7e0 (diff) | |
net: phy: hack for Lion v2.0: enable VSC8531 125 MHz clock output
We need the phy to generate the 125 mhz clock, and there does not
seem to be a way to activiate it via the DTS. Hardcode it for now.
After this patch, ethernet works fine:
root@rk3368-uq7:~# iperf -c crompton.lan
------------------------------------------------------------
Client connecting to crompton.lan, TCP port 5001
TCP window size: 85.0 KByte (default)
------------------------------------------------------------
[ 3] local 10.2.191.136 port 36070 connected with 10.2.0.1 port 5001
[ ID] Interval Transfer Bandwidth
[ 3] 0.0-10.0 sec 1.09 GBytes 939 Mbits/sec
Signed-off-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
| -rw-r--r-- | drivers/net/phy/mscc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c index b4cbc697db54..857725aca7e4 100644 --- a/drivers/net/phy/mscc.c +++ b/drivers/net/phy/mscc.c @@ -452,6 +452,20 @@ static int vsc85xx_default_config(struct phy_device *phydev) reg_val |= (RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS); phy_write(phydev, MSCC_PHY_RGMII_CNTL, reg_val); rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); + if (rc != 0) + goto out_unlock; + + + /* hack for Lion v2.0: enable VSC8531 125 MHz clock output */ + rc = vsc85xx_phy_page_set(phydev, 16); + if (rc != 0) + goto out_unlock; + phy_write(phydev, 13, 0xc000); + rc = vsc85xx_phy_page_set(phydev, MSCC_PHY_PAGE_STANDARD); + if (rc != 0) + goto out_unlock; + phydev_err(phydev, "enabled 125 mhz clock output\n"); + /* end hack */ out_unlock: mutex_unlock(&phydev->lock); |