summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChristoph Muellner <christoph.muellner@theobroma-systems.com>2019-06-13 13:21:36 +0200
committerChristoph Muellner <christoph.muellner@theobroma-systems.com>2019-10-02 00:39:48 +0200
commitd9df52d08ab897097368e85e2fc5567777df3d67 (patch)
treeadf2b2b5788f42c895af649afc32ddea733b3677
parente149d33aecae8a842ac0fac7dda13cbe552cd12a (diff)
dts: rk3368: Remove links to eFuse information.
The operating point description of the RK3368 contains links to eFuse information in order to adjust the OPs according to actual SoC characteristics, which can be read out from the eFuses. However, the read-out of eFuse information is only possible from secure mode. Therefore this information has be fetched via SMC calls. The current implementation to get these information requires transparent read/write access to the (secure) eFuse block. I.e. function calls sip_smc_secure_reg_write() and sip_smc_secure_reg_read(). This approach has several disadvantages: 1) security of the secure eFuse block is completely undermined, 2) no implementation in upstream ATF/Optee. As there is no robust solution to read out the required information, we simply drop the feature with the effect, that the worst characteristics of the SoC are assumed. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 4ac03425761e..e3ae59c83d0a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -224,8 +224,6 @@
1 24 0
25 254 1
>;
- nvmem-cells = <&cpu_leakage>;
- nvmem-cell-names = "cpu_leakage";
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
@@ -286,8 +284,6 @@
25 50 1
51 254 2
>;
- nvmem-cells = <&cpu_leakage>;
- nvmem-cell-names = "cpu_leakage";
opp-216000000 {
opp-hz = /bits/ 64 <216000000>;
@@ -769,8 +765,6 @@
clock-frequency = <32768>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- nvmem-cells = <&temp_adjust>;
- nvmem-cell-names = "temp_adjust";
#thermal-sensor-cells = <1>;
hw-shut-temp = <95000>;
latency-bound = <50000>;