diff options
| author | Brian Norris <briannorris@chromium.org> | 2018-03-09 17:12:21 -0800 |
|---|---|---|
| committer | Tao Huang <huangtao@rock-chips.com> | 2019-03-12 16:09:22 +0800 |
| commit | c7acb7de6674ce5fb109215e74d7f88eb9c791a8 (patch) | |
| tree | 532aacddf4a0816e2a3e3d61e88ce855048faa17 | |
| parent | afdc278b1822de0ddcdbc164278e500563cf1c52 (diff) | |
FROMLIST: watchdog: dw: RMW the control register
RK3399 has rst_pulse_length in CONTROL_REG[4:2], determining the length
of pulse to issue for system reset. We shouldn't clobber this value,
because that might make the system reset ineffective. On RK3399, we're
seeing that a value of 000b (meaning 2 cycles) yields an unreliable
(partial?) reset, and so we only fully reset after the watchdog fires a
second time. If we retain the system default (010b, or 8 clock cycles),
then the watchdog reset is much more reliable.
Read-modify-write retains the system value and improves reset
reliability.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
(am from https://patchwork.kernel.org/patch/10273163/)
Conflicts:
core watchdog frameworks were reworked, so this moved from an
open() function to a start() function
BUG=b:74204857
TEST=force watchdog event before/after suspend/resume on kevin and scarlet;
check timing
Reviewed-on: https://chromium-review.googlesource.com/958088
Commit-Ready: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Change-Id: I18d5ec3604a44a671ba79ceea1821e733bf051fe
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
| -rw-r--r-- | drivers/watchdog/dw_wdt.c | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c index 059c9746f5f7..a2edcef2c13d 100644 --- a/drivers/watchdog/dw_wdt.c +++ b/drivers/watchdog/dw_wdt.c @@ -41,6 +41,7 @@ #define WDOG_CONTROL_REG_OFFSET 0x00 #define WDOG_CONTROL_REG_WDT_EN_MASK 0x01 +#define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02 #define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4 #define WDOG_CURRENT_COUNT_REG_OFFSET 0x08 @@ -139,19 +140,26 @@ static int dw_wdt_set_top(unsigned top_s) return dw_wdt_top_in_seconds(top_val); } +static void dw_wdt_arm_system_reset(void) +{ + u32 val = readl(dw_wdt.regs + WDOG_CONTROL_REG_OFFSET); + + /* Disable interrupt mode; always perform system reset. */ + val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK; + /* Enable watchdog. */ + val |= WDOG_CONTROL_REG_WDT_EN_MASK; + writel(val, dw_wdt.regs + WDOG_CONTROL_REG_OFFSET); +} + static int dw_wdt_restart_handle(struct notifier_block *this, unsigned long mode, void *cmd) { - u32 val; - writel(0, dw_wdt.regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); - val = readl(dw_wdt.regs + WDOG_CONTROL_REG_OFFSET); - if (val & WDOG_CONTROL_REG_WDT_EN_MASK) + if (dw_wdt_is_enabled()) writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt.regs + WDOG_COUNTER_RESTART_REG_OFFSET); else - writel(WDOG_CONTROL_REG_WDT_EN_MASK, - dw_wdt.regs + WDOG_CONTROL_REG_OFFSET); + dw_wdt_arm_system_reset(); /* wait for reset to assert... */ mdelay(500); @@ -183,8 +191,7 @@ static int dw_wdt_open(struct inode *inode, struct file *filp) * something reasonable and then start it. */ dw_wdt_set_top(DW_WDT_DEFAULT_SECONDS); - writel(WDOG_CONTROL_REG_WDT_EN_MASK, - dw_wdt.regs + WDOG_CONTROL_REG_OFFSET); + dw_wdt_arm_system_reset(); } dw_wdt_set_next_heartbeat(); |